| Name | Data Type | Default Value | Qualifiers |
| Name | Data Type | Value |
| BridgeType | uint16 | |
| Description | string | The type of bridge. Except for "Host" (value=0) and "PCIe-to-PCI" (value=10), the type of bridge is PCI-to-<value>. For type "Host", the device is a Host-to-PCI bridge. For type "PCIe-to-PCI", the device is a PCI Express-to-PCI bridge. |
| ValueMap | string | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 128, .. |
| Values | string | Host, ISA, EISA, Micro Channel, PCI, PCMCIA, NuBus, CardBus, RACEway, AGP, PCIe, PCIe-to-PCI, Other, DMTF Reserved |
| IOBase | uint8 | |
| Description | string | Base address of I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 0. |
| IOBaseUpper16 | uint16 | |
| Description | string | Upper 16 bits of the supported I/O base address when 32-bit I/O addressing is used. The lower 16 bits are assumed to be 0. |
| IOLimit | uint8 | |
| Description | string | End address of the I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 1. |
| IOLimitUpper16 | uint16 | |
| Description | string | Upper 16 bits of the supported I/O end address when 32-bit I/O addressing is used. The lower 16 bits are each assumed to be 1. |
| MemoryBase | uint16 | |
| Description | string | Base address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0. |
| MemoryLimit | uint16 | |
| Description | string | End address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1. |
| PrefetchBaseUpper32 | uint32 | |
| Description | string | Upper 32 bits of the supported prefetch base address when 64-bit addressing is used. The lower 32 bits are assumed to be 0. |
| PrefetchLimitUpper32 | uint32 | |
| Description | string | Upper 32 bits of the supported prefetch end address when 64-bit addressing is used. The lower 32 bits are each assumed to be 1. |
| PrefetchMemoryBase | uint16 | |
| Description | string | Base address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0. |
| PrefetchMemoryLimit | uint16 | |
| Description | string | End address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1. |
| PrimaryBusNumber | uint8 | |
| Description | string | The number of the PCI bus segment to which the primary interface of the bridge is connected. |
| SecondaryBusDeviceSelectTiming | uint16 | |
| Description | string | The slowest device-select timing for a target device on the secondary bus. |
| ValueMap | string | 0, 1, 2, 3, 4, 5 |
| Values | string | Unknown, Other, Fast, Medium, Slow, DMTF Reserved |
| SecondaryLatencyTimer | uint8 | |
| Description | string | The timeslice for the secondary interface when the bridge is acting as an initiator. A 0 value indicates no requirement. |
| PUnit | string | cycle |
| Units | string | PCI clock cycles |
| SecondaryStatusRegister | uint16 | |
| Description | string | The contents of the SecondaryStatusRegister of the Bridge. For more information on the contents of this register, refer to the PCI-to-PCI Bridge Architecture Specification. |
| SecondayBusNumber | uint8 | |
| Description | string | The number of the PCI bus segment to which the secondary interface of the bridge is connected. |
| SubordinateBusNumber | uint8 | |
| Description | string | The number of the highest numbered bus that exists behind the bridge. |