Class CIM_PCIBridge
extends CIM_PCIDevice

Capabilities and management of a PCI controller that provide bridge-to-bridge capability.

Table of Contents
Hierarchy
Direct Known Subclasses
Class Qualifiers
Class Properties
Class Methods


Class Hierarchy

CIM_ManagedElement
   |
   +--CIM_ManagedSystemElement
   |
   +--CIM_LogicalElement
   |
   +--CIM_EnabledLogicalElement
   |
   +--CIM_LogicalDevice
   |
   +--CIM_Controller
   |
   +--CIM_PCIController
   |
   +--CIM_PCIDevice
   |
   +--CIM_PCIBridge

Direct Known Subclasses

Class Qualifiers

NameData TypeValue
DescriptionstringCapabilities and management of a PCI controller that provide bridge-to-bridge capability.
UMLPackagePathstringCIM::Device::Controller
Versionstring2.22.0

Class Properties

Local Class Properties

NameData TypeDefault ValueQualifiers
NameData TypeValue
BridgeTypeuint16
DescriptionstringThe type of bridge. Except for "Host" (value=0) and "PCIe-to-PCI" (value=10), the type of bridge is PCI-to-<value>. For type "Host", the device is a Host-to-PCI bridge. For type "PCIe-to-PCI", the device is a PCI Express-to-PCI bridge.
ValueMapstring0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 128, ..
ValuesstringHost, ISA, EISA, Micro Channel, PCI, PCMCIA, NuBus, CardBus, RACEway, AGP, PCIe, PCIe-to-PCI, Other, DMTF Reserved
IOBaseuint8
DescriptionstringBase address of I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 0.
IOBaseUpper16uint16
DescriptionstringUpper 16 bits of the supported I/O base address when 32-bit I/O addressing is used. The lower 16 bits are assumed to be 0.
IOLimituint8
DescriptionstringEnd address of the I/O addresses supported by the bus. The upper 4 bits of this property specify the address bits, AD[15::12], of the I/O address. Each of the remaining 12 bits of the I/O address are assumed to be 1.
IOLimitUpper16uint16
DescriptionstringUpper 16 bits of the supported I/O end address when 32-bit I/O addressing is used. The lower 16 bits are each assumed to be 1.
MemoryBaseuint16
DescriptionstringBase address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0.
MemoryLimituint16
DescriptionstringEnd address of the memory supported by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1.
PrefetchBaseUpper32uint32
DescriptionstringUpper 32 bits of the supported prefetch base address when 64-bit addressing is used. The lower 32 bits are assumed to be 0.
PrefetchLimitUpper32uint32
DescriptionstringUpper 32 bits of the supported prefetch end address when 64-bit addressing is used. The lower 32 bits are each assumed to be 1.
PrefetchMemoryBaseuint16
DescriptionstringBase address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 0.
PrefetchMemoryLimituint16
DescriptionstringEnd address of the memory that can be prefetched by the bus. The upper 12 bits of this property specify the address bits, AD[31::20], of a 32-bit memory address. Each of the remaining 20 bits of the address are assumed to be 1.
PrimaryBusNumberuint8
DescriptionstringThe number of the PCI bus segment to which the primary interface of the bridge is connected.
SecondaryBusDeviceSelectTiminguint16
DescriptionstringThe slowest device-select timing for a target device on the secondary bus.
ValueMapstring0, 1, 2, 3, 4, 5
ValuesstringUnknown, Other, Fast, Medium, Slow, DMTF Reserved
SecondaryLatencyTimeruint8
DescriptionstringThe timeslice for the secondary interface when the bridge is acting as an initiator. A 0 value indicates no requirement.
PUnitstringcycle
UnitsstringPCI clock cycles
SecondaryStatusRegisteruint16
DescriptionstringThe contents of the SecondaryStatusRegister of the Bridge. For more information on the contents of this register, refer to the PCI-to-PCI Bridge Architecture Specification.
SecondayBusNumberuint8
DescriptionstringThe number of the PCI bus segment to which the secondary interface of the bridge is connected.
SubordinateBusNumberuint8
DescriptionstringThe number of the highest numbered bus that exists behind the bridge.

Inherited Properties

NameData TypeClass Origin
Availabilityuint16CIM_LogicalDevice
BusNumberuint8CIM_PCIDevice
CacheLineSizeuint8CIM_PCIController
CaptionstringCIM_ManagedElement
ClassCodeuint8CIM_PCIController
CommandRegisteruint16CIM_PCIController
CommunicationStatusuint16CIM_ManagedSystemElement
CreationClassNamestringCIM_LogicalDevice
DescriptionstringCIM_ManagedElement
DetailedStatusuint16CIM_ManagedSystemElement
DeviceIDstringCIM_LogicalDevice
DeviceNumberuint8CIM_PCIDevice
DeviceSelectTiminguint16CIM_PCIController
ElementNamestringCIM_ManagedElement
EnabledDefaultuint16CIM_EnabledLogicalElement
EnabledStateuint16CIM_EnabledLogicalElement
ErrorClearedbooleanCIM_LogicalDevice
ErrorDescriptionstringCIM_LogicalDevice
ExpansionROMBaseAddressuint32CIM_PCIController
FunctionNumberuint8CIM_PCIDevice
Generationuint64CIM_ManagedElement
HealthStateuint16CIM_ManagedSystemElement
InstallDatedatetimeCIM_ManagedSystemElement
InstanceIDstringCIM_ManagedElement
InterruptPinuint16CIM_PCIController
LastErrorCodeuint32CIM_LogicalDevice
LatencyTimeruint8CIM_PCIController
LocationIndicatoruint16CIM_LogicalDevice
MaxLatencyuint8CIM_PCIDevice
MaxNumberControlleduint32CIM_Controller
MaxQuiesceTimeuint64CIM_LogicalDevice
MinGrantTimeuint8CIM_PCIDevice
NamestringCIM_ManagedSystemElement
OperatingStatusuint16CIM_ManagedSystemElement
OtherEnabledStatestringCIM_EnabledLogicalElement
PCIDeviceIDuint16CIM_PCIDevice
PowerManagementSupportedbooleanCIM_LogicalDevice
PowerOnHoursuint64CIM_LogicalDevice
PrimaryStatusuint16CIM_ManagedSystemElement
ProtocolDescriptionstringCIM_Controller
ProtocolSupporteduint16CIM_Controller
RequestedStateuint16CIM_EnabledLogicalElement
RevisionIDuint8CIM_PCIDevice
SelfTestEnabledbooleanCIM_PCIController
StatusstringCIM_ManagedSystemElement
StatusInfouint16CIM_LogicalDevice
SubsystemIDuint16CIM_PCIDevice
SubsystemVendorIDuint16CIM_PCIDevice
SystemCreationClassNamestringCIM_LogicalDevice
SystemNamestringCIM_LogicalDevice
TimeOfLastResetdatetimeCIM_Controller
TimeOfLastStateChangedatetimeCIM_EnabledLogicalElement
TotalPowerOnHoursuint64CIM_LogicalDevice
TransitioningToStateuint16CIM_EnabledLogicalElement
VendorIDuint16CIM_PCIDevice
AdditionalAvailabilityuint16[]CIM_LogicalDevice
AvailableRequestedStatesuint16[]CIM_EnabledLogicalElement
BaseAddressuint32[]CIM_PCIDevice
BaseAddress64uint64[]CIM_PCIDevice
Capabilitiesuint16[]CIM_PCIController
CapabilityDescriptionsstring[]CIM_PCIController
IdentifyingDescriptionsstring[]CIM_LogicalDevice
OperationalStatusuint16[]CIM_ManagedSystemElement
OtherIdentifyingInfostring[]CIM_LogicalDevice
PowerManagementCapabilitiesuint16[]CIM_LogicalDevice
StatusDescriptionsstring[]CIM_ManagedSystemElement

Class Methods

Inherited Class Methods

NameReturn TypeClass Origin
BISTExecutionuint8CIM_PCIController
EnableDeviceuint32CIM_LogicalDevice
OnlineDeviceuint32CIM_LogicalDevice
QuiesceDeviceuint32CIM_LogicalDevice
RequestStateChangeuint32CIM_EnabledLogicalElement
Resetuint32CIM_LogicalDevice
RestorePropertiesuint32CIM_LogicalDevice
SavePropertiesuint32CIM_LogicalDevice
SetPowerStateuint32CIM_LogicalDevice