| Name | Data Type | Default Value | Qualifiers |
| Name | Data Type | Value |
| CacheLineSize | uint8 | |
| Description | string | Specifies the system cache line size in doubleword increments (for example, a 486-based system would store the value 04h, indicating a cache line size of four doublewords. |
| PUnit | string | dataword * 2 |
| Units | string | DoubleWords |
| ClassCode | uint8 | |
| Description | string | Register of 8 bits that identifies the basic function of the PCI device. This property is only the upper byte (offset 0Bh) of the 3-byte ClassCode field. Note that the ValueMap array of the property specifies the decimal representation of this information. |
| ValueMap | string | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18..254, 255 |
| Values | string | Pre 2.0, Mass Storage, Network, Display, Multimedia, Memory, Bridge, Simple Communications, Base Peripheral, Input, Docking Station, Processor, Serial Bus, Wireless, Intelligent I/O, Satellite Communication, Encryption/Decryption, Data Acquisition and Signal Processing, PCI Reserved, Other |
| CommandRegister | uint16 | |
| Description | string | Current contents of the register that provides basic control over the ability of the device to respond to or perform PCI accesses. |
| DeviceSelectTiming | uint16 | |
| Description | string | The slowest device-select timing for a target device. |
| ValueMap | string | 0, 1, 2, 3, 4, 5 |
| Values | string | Unknown, Other, Fast, Medium, Slow, Reserved |
| ExpansionROMBaseAddress | uint32 | |
| Description | string | Doubleword Expansion ROM-base memory address. |
| PUnit | string | dataword * 2 |
| Units | string | DoubleWords |
| InterruptPin | uint16 | |
| Description | string | Defines the PCI interrupt request pin (INTA# to INTD#) to which a PCI functional device is connected. |
| ValueMap | string | 0, 1, 2, 3, 4, 5 |
| Values | string | None, INTA#, INTB#, INTC#, INTD#, Unknown |
| LatencyTimer | uint8 | |
| Description | string | Defines the minimum amount of time, in PCI clock cycles, that the bus master can retain ownership of the bus. |
| PUnit | string | cycle |
| Units | string | PCI clock cycles |
| SelfTestEnabled | boolean | |
| Description | string | Reports if the PCI device can perform the self-test function. Returns bit 7 of the BIST register as a Boolean. |
| Capabilities | uint16[] | |
| ArrayType | string | Indexed |
| Description | string | An array of integers that indicates controller capabilities. Information such as "Supports 66MHz" (value=2) is specified in this property. The data in the Capabilities array is gathered from the PCI Status Register and the PCI Capabilities List as defined in the PCI Specification. |
| ModelCorrespondence | string | CIM_PCIController.CapabilityDescriptions |
| ValueMap | string | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18..32767, 32768..65535 |
| Values | string | Unknown, Other, Supports 66MHz, Supports User Definable Features, Supports Fast Back-to-Back Transactions, PCI-X Capable, PCI Power Management Supported, Message Signaled Interrupts Supported, Parity Error Recovery Capable, AGP Supported, Vital Product Data Supported, Provides Slot Identification, Hot Swap Supported, Supports PCIe, Supports PCIe Gen 2, Supports PCIe Gen 3, Supports PCIe Gen 4, Supports PCIe Gen 5, DMTF Reserved, Vendor Reserved |
| CapabilityDescriptions | string[] | |
| ArrayType | string | Indexed |
| Description | string | An array of free-form strings that provides more detailed explanations for any of the PCIController features that are indicated in the Capabilities array. Note, each entry of this array is related to the entry in the Capabilities array that is located at the same index. |
| ModelCorrespondence | string | CIM_PCIController.Capabilities |